Current computer systems rely heavily on the performance of RAM memory devices. However, there is a bottleneck at the computer interface between a host processor and the RAM that causes undesirable latency even with the most advanced memory architectures. Furthermore, for state-of-the-art RAM technology, system performance may depend strongly on both the application being executed, and the data traffic profile between the host processor and the RAM. While increasing RAM frequency and buffer space at the controller interface may provide partial performance improvement, these approaches are power consuming and also tend to occupy device space in the controller, which is undesirable.
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